1. Technical Field
This invention generally relates to the field of semiconductor processing and integrated circuit manufacturing. More specifically, the present invention relates to a process for locating defective integrated circuit devices.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country, in appliances, in televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependent on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers.
Integrated circuits are chemically and physically integrated into a substrate material, such as a silicon or gallium arsenide wafer, by combining electrically conductive, semi-conductive, and dielectric (insulating) layers or regions. The layers and regions are arranged to form electronic components or devices such as transistors, diodes, and capacitors. Millions of these devices are formed essentially simultaneously on the surface of a single wafer of semiconductor material during processing. Given the intricate nature of the fabrication process and the large number of devices formed during the typical fabrication process, it should not be surprising to note that certain defects can be introduced into the integrated circuits during the fabrication process.
Defects in integrated circuit structures may be caused by many factors. Some defects are due to imperfections in the underlying semiconductor crystalline structure while others are caused by imperfections in the physical structure of the circuit components and connections. For instance, a "dislocation" is a physical defect in the structure of the semiconductor crystal (typically silicon) at a very small scale. A dislocation may involve as few as four or five silicon atoms oriented differently than the other atoms in the crystal. A dislocation can impair the electrical function of a chip by causing threshold voltage shifts or leakage current. However, due to the nature of most dislocations, a dislocation is not easily detected. In addition, since the electrical activity of a dislocation defect can increase with the passage of time, the continued application of heat and voltage after fabrication can cause circuit failure.
In addition to those defects mentioned above, other defects may occur at contact points within a circuit or module. A contact point is the region located at the top or bottom of an opening between layers that allows an electrical contact to be made to individual layers. These contact points may become stressed during the fabrication process and develop an undesirable resistance to the passage of electrical current that may ultimately impede circuit performance. Ideally, these contact points will transmit an electrical current or signal with very little or no resistance. However, as these contact points develop increased resistance, they may eventually prevent the components within an integrated circuit from responding correctly. In an extreme case, a contact point may be so damaged as to create an open circuit, leading to an inoperative circuit or device. Damage to the contact points may be caused by stresses such as heating and cooling.
Another type of defect that can adversely affect circuit performance is called a "stacking fault." A stacking fault occurs when there are localized partial displacements of close-packed silicon planes that upset the normal crystal lattice structure. Stacking faults are common in integrated circuits and tend to increase as the device density increases.
Yet another common defect is known as a "high resistance strap." In general, a strap is a layer of doped polysilicon that is used as an interconnection between components of a chip. A strap may have a constriction or crack in the polysilicon that results in the strap having a higher than normal resistance.
Typically, in order to find defects in an integrated circuit, various types of "burn-in" testing can be performed. Burn-in testing consists of subjecting a circuit to a higher than normal voltage and temperature to stress the circuit components. Burn-in testing can be performed directly in-situ on the wafer, or at a later time such as when the individual integrated circuits have been packaged and incorporated into a finished module, component, or product. For example, once a wafer has been processed, the overall wafer is tested for defects. A probe device is connected to the contact pads for each die located on the periphery of the individual integrated circuits. This allows each integrated circuit to be connected to an electrical source and a reference ground to supply an operational current. The wafer is typically tested at voltage levels approximately 1.5 times the rated nominal value. For example, a typical circuit on a wafer may be designed to operate with a supplied voltage level of approximately 3.3 volts. Therefore, in this specific example of burn-in testing, the circuit will be operated at a voltage level of approximately 5-6 volts. This enhanced voltage level will create a flow of electricity and enhanced electric fields throughout the circuit which are greater than normal. While this stress is greater than the stress applied to the circuits during normal operations, the applied levels of current and the resulting electrical fields are controlled during burn-in testing so that they will not adversely affect the integrated circuit, but will only trigger defects so that they may be located and eliminated.
During the burn-in testing period, the circuitry on the wafer is electrically "exercised" or tested. However, due to the nature of certain defects, many of the defects listed above may not be readily apparent during standard burn-in testing. This is because the effects of many common defects increase only with the passage of time, or with the continued application of heat and/or voltage to the affected components.
There exists, therefore, a need to improve burn-in to identify additional defects to improve the reliability of the devices that are shipped to customers. Such a method would be financially beneficial to semiconductor manufacturers and would increase customer satisfaction in semiconductor products.